Multilayer capacitor built-in substrate

ABSTRACT

A multilayer capacitor built-in substrate includes a core substrate, a multilayer capacitor mounted on one principal surface of the core substrate, and a burying layer provided on the one principal surface of the core substrate to bury the multilayer capacitor. The multilayer capacitor includes a laminated body in which dielectric layers and internal electrode layers are laminated, and first and second external electrodes. The laminated body includes an effective region in which internal electrode layers respectively connected to the first external electrode and the second external electrode are laminated with a dielectric layer located therebetween, and a non-effective region surrounding the effective region. The core substrate includes, on the one principal surface, a first land electrode electrically connected to the first external electrode and a second land electrode electrically connected to the second external electrode.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority to Japanese Patent Application No. 2016-235742 filed on Dec. 5, 2016. The entire contents of this application are hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a multilayer capacitor built-in substrate.

2. Description of the Related Art

In recent years, as the performance of electronic devices has been increased, the capacitance of multilayer ceramic capacitors has been increased progressively.

In the case of high-capacitance multilayer ceramic capacitors, high dielectric constant ceramic materials such as barium titanate, have been used as a dielectric material.

These high dielectric constant ceramic materials include piezoelectric and electrostrictive properties, and thus, in multilayer ceramic capacitors including dielectrics composed of the high dielectric constant ceramic materials, mechanical distortion will be produced when a voltage is applied.

Therefore, when an alternating-current voltage or a direct-current voltage with an alternating-current component superimposed thereon is applied to the multilayer ceramic capacitors mounted on circuit boards, vibrations will be generated in the multilayer ceramic capacitor due to distortion of the multilayer ceramic capacitors, and the vibrations will propagate to the circuit boards, thereby vibrating the circuit boards.

In this regard, when the circuit board vibrates at a frequency of 20 Hz to 20,000 Hz in the audible frequency range due to the propagated vibration, noise referred to as “acoustic noise” will be generated.

Various proposals have been made as techniques to reduce the noise described above. For example, in the multilayer ceramic capacitor described in Japanese Patent Application Laid-Open No. 2015-65414, a capacitor main body integrally includes a capacitance part, an upper protection part, and a lower protection part, and the thickness of the lower protection part is larger than the thickness of the upper protection part so that the capacitance part is positioned on the upper side in the height direction of the capacitor main body. In addition, in the multilayer ceramic capacitor described in Japanese Patent Application Laid-Open No. 2015-226026, a capacitor main body includes a first protection part, a capacitance part, an electrostrictive relaxation part, a characteristic adjustment part, and a second protection part provided in layers in the height direction, and when the thickness of the capacitance part, the thickness of the electrostrictive relaxation part, and the thickness of the characteristic adjustment part are denoted respectively by T2, T3, and T4, the condition of T2>T3>T4 is satisfied. Furthermore, in the multilayer ceramic capacitor described in Japanese Patent Application Laid-Open No. 2016-127045, a capacitor main body includes a first protection part, a capacitance part, and a second protection part provided in layers in this order in the height direction, the capacitor part includes a high capacitance part and a low capacitance part continuously in the height direction, and the opposed interval between n2 layers of internal electrode layers included in the low capacitance part is larger than the opposed interval between n1 layers of internal electrode layers included in the high capacitance part.

In recent years, electronic component built-in substrates have been proposed in which electronic components such as, multilayer ceramic capacitors, are buried in the substrates, thereby achieving reductions in substrate thickness. However, when the multilayer ceramic capacitors described in Japanese Patent Application Laid-Open No. 2015-65414, Japanese Patent Application Laid-Open No. 2015-226026, and Japanese Patent Application Laid-Open No. 2016-127045 are mounted on substrates, and the multilayer ceramic capacitors are buried in burying layers including a resin, the burying layers are also believed to propagate distortion of the multilayer ceramic capacitors to the substrates. As a result, there is a concern that the vibrations of the substrates will be increased, thereby making it difficult to suppress acoustic noise.

SUMMARY OF THE INVENTION

Preferred embodiments of the present invention provide multilayer capacitor built-in substrates that are able to significantly reduce or prevent acoustic noise.

A multilayer capacitor built-in substrate according to a preferred embodiment the present invention is a multilayer capacitor built-in substrate including a core substrate, a multilayer capacitor mounted on one principal surface of the core substrate, and a burying layer provided on the one principal surface of the core substrate to bury the multilayer capacitor. The multilayer capacitor includes a laminated body with a plurality of dielectric layers and a plurality of internal electrode layers laminated, a first external electrode, and a second external electrode. The laminated body includes a first principal surface opposed in a thickness direction orthogonal or substantially orthogonal to the one principal surface of the core substrate, a second principal surface opposed in the thickness direction orthogonal or substantially orthogonal to the one principal surface of the core substrate and opposed to the one principal surface of the core substrate, a first end surface and a second end surface opposed in a length direction orthogonal or substantially orthogonal to the thickness direction, and a first side surface and a second side surface opposed in a width direction orthogonal or substantially orthogonal to the thickness direction and the length direction. The first external electrode is provided on the first end surface of the laminated body and electrically connected to at least some of the internal electrode layers of the plurality of internal electrode layers, and the second external electrode is provided on the second end surface of the laminated body and electrically connected to at least some of the internal electrode layers of the plurality of internal electrode layers The laminated body includes an effective region where the internal electrode layers respectively connected to the first external electrode and the second external electrode are laminated with the dielectric layers located therebetween, and a non-effective region surrounding the effective region. The core substrate includes on the one principal surface, a first land electrode electrically connected to the first external electrode, and a second land electrode electrically connected to the first external electrode. A thickness T_(R) of the burying layer is larger than a thickness T_(B) of the core substrate, and T_(C)<L_(L)/4 is satisfied when a distance between the first land electrode and the second land electrode in the length direction is denoted by L_(L), and a height of a center of the effective region with the second principal surface of the laminated body as a reference plane is denoted by T_(C).

According to a preferred embodiment of the present invention, the height T_(C) of the center of the effective region is about ¼ or less of the thickness T_(R) of the burying layer.

According to a preferred embodiment of the present invention, the value of T/W is preferably about ¾ or less when a thickness of the laminated body and a width of the laminated body are denoted respectively T and W.

According to a preferred embodiment of the present invention, the thickness T of the laminated body is preferably about 0.33 mm or less.

According to a preferred embodiment of the present invention, the thickness T_(a) of the non-effective region closer to the second principal surface is smaller than the thickness T_(b) of the non-effective region closer to the first principal surface.

Preferred embodiments of the present invention provide multilayer capacitor built-in substrates that are able to significantly reduce or prevent acoustic noise.

The above and other elements, features, steps, characteristics and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view schematically illustrating a multilayer capacitor built-in substrate according to a preferred embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line X1-X1 of a multilayer capacitor built-in substrate according to a first preferred embodiment of the present invention.

FIG. 3 is a cross-sectional view taken along the line Y1-Y1 of the multilayer capacitor built-in substrate according to the first preferred embodiment of the present invention.

FIG. 4 is a cross-sectional view schematically illustrating an imaginary multilayer capacitor built-in substrate.

FIG. 5 is a cross-sectional view taken along the line X1-X1 of a multilayer capacitor built-in substrate according to a second preferred embodiment of the present invention.

FIG. 6 is a cross-sectional view taken along the line Y1-Y1 of the multilayer capacitor built-in substrate according to the second preferred embodiment of the present invention.

FIGS. 7A, 7B and 7C are explanatory diagrams schematically illustrating an effective region and a non-effective region of a laminated body of a multilayer ceramic capacitor.

FIG. 8 is a schematic diagram illustrating a method of measuring the sound pressure of noise generated from a multilayer capacitor built-in substrate.

FIG. 9 is a graph showing the results of measuring the sound pressure of noise in Preferred Embodiment Example 1-1, Preferred Embodiment Example 1-2, Preferred Embodiment Example 1-3, Preferred Embodiment Example 1-4, and Comparative Example 1-1.

FIG. 10 is a graph showing the results of measuring the sound pressure of noise in Preferred Embodiment Example 1-5, Preferred Embodiment Example 1-6, and Comparative Example 1-2.

FIG. 11 is a graph showing the results of measuring the sound pressure of noise in Preferred Embodiment Example 2-1 and Comparative Example 2-1.

FIG. 12 is a graph showing the results of measuring the sound pressure of noise in Preferred Embodiment Example 2-2 and Comparative Example 2-2.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In multilayer capacitor built-in substrates according to preferred embodiments of the present invention, a thickness T_(R) of a burying layer is larger than a thickness T_(B) of a core substrate. Furthermore, T_(C)<L_(L)/4 is satisfied when the distance between a first land electrode and a second land electrode in the length direction is denoted by L_(L), and the height of the center of an effective region with a second principal surface of a laminated body as a reference plane is denoted by T_(C).

Multilayer capacitor built-in substrates according to the preferred embodiments of the present invention will be described below.

However, the preferred embodiments of the present invention are not to be considered limited to the following specific features, elements, and components, but are able to be applied with changes appropriately made without changing the scope of the present invention. It is to be noted that the preferred embodiments of the present invention also encompass combinations of two or more individual preferred embodiments of the present invention as described below.

The following respective preferred embodiments of the present invention are considered by way of example, and it is possible to partially substitute or combine specific features, elements, and components presented in different preferred embodiments with one another. In a second preferred embodiment and the subsequent sections, descriptions of common matters with a first preferred embodiment will be omitted, and only differences will be described. Particularly, the similar features and effects provided by similar features, elements, and components will not be mentioned sequentially for each preferred embodiment.

In the following preferred embodiments of the present invention, cases where the multilayer capacitor is a multilayer ceramic capacitor will be described, but the dielectric material of the multilayer capacitor is not limited to any ceramic material as long as distortion is able to be generated by application of a voltage. For example, preferred embodiments of the present invention are able to be also applied to a multilayer-type metallized film capacitor, which is a multilayer capacitor that includes a resin material as a dielectric material other than a ceramic material.

First Preferred Embodiment

According to a first preferred embodiment of the present invention, the height T_(C) of the center of the effective region is about ¼ or less of the thickness T_(R) of the burying layer, for example.

FIG. 1 is a top view schematically illustrating a multilayer capacitor built-in substrate according to a preferred embodiment the present invention.

FIG. 2 is a cross-sectional view taken along the line X1-X1 of a multilayer capacitor built-in substrate according to a first preferred embodiment of the present invention. FIG. 3 is a cross-sectional view taken along the line Y1-Y1 of the multilayer capacitor built-in substrate according to the first preferred embodiment. It is to be noted that FIG. 2 corresponds to the cross-sectional view taken along the line X1-X1 of the multilayer capacitor built-in substrate shown in FIG. 1, and FIG. 3 corresponds to the cross-sectional view taken along the line Y1-Y1 of the multilayer capacitor built-in substrate shown in FIG. 1.

The multilayer capacitor built-in substrate 1 shown in FIGS. 2 and 3 includes a core substrate B, a multilayer ceramic capacitor 10, and a burying layer R. The multilayer ceramic capacitor 10 is mounted on one principal surface of a core substrate B that includes one principal surface and the other principal surface parallel or substantially parallel to each other within the error range. The burying layer R is provided on one principal surface of the core substrate B to bury the multilayer ceramic capacitor 10, and to cause the outer surface to be parallel or substantially parallel to the other principal surface of the core substrate B within the error range.

The length direction L, the width direction W, and the thickness direction T of the multilayer ceramic capacitor 10 are shown in FIGS. 2 and 3. In this regard, the length direction L, the width direction W, and the thickness direction T are orthogonal or substantially orthogonal to each other. The thickness direction T is a direction orthogonal or substantially orthogonal to one principal surface of the core substrate B.

In the multilayer capacitor built-in substrate 1 shown in FIGS. 2 and 3, the burying layer R includes a resin material portion.

The resin material portion includes a resin material that includes a glass material, silica, or the like dispersed as a filler. Although not shown in FIGS. 2 and 3, the burying layer R may further include, in addition to the resin material portion, a conductive material portion provided on the surface of the resin material portion.

The core substrate B is provided, on one principal surface thereof, with a first land electrode L11 and a second land electrode L12. The core substrate B is, for example, a multilayer substrate, and shown in a simplified fashion without internal electrodes, vias, etc. shown. It is to be noted that in FIGS. 2 and 3, in order to highlight the multilayer ceramic capacitor 10, the relationship between the sizes of the core substrate B and the multilayer ceramic capacitor 10 is different from the actual relationship.

The multilayer ceramic capacitor 10 includes a laminated body 11 in which a plurality of dielectric layers 14 and a plurality of internal electrode layers 15 or 16 are alternately laminated, and a first external electrode 12 and a second external electrode 13 provided on the laminated body 11 and located on surfaces at both ends in the length direction L. According to the present preferred embodiment, the multilayer ceramic capacitor preferably includes two external electrodes, for example. However, multilayer capacitor built-in substrates according to other preferred embodiments of the present invention, the multilayer capacitor may include at least two external electrodes.

According to the present preferred embodiment, the laminating direction of the dielectric layers 14 and the internal electrode layers 15 or 16 is orthogonal or substantially orthogonal to the length direction L and the width direction W of the multilayer ceramic capacitor 10. More specifically, the laminating direction of the dielectric layers 14 and the internal electrode layers 15 or 16 is parallel or substantially parallel to the thickness direction T of the multilayer ceramic capacitor 10.

The laminated body 11 includes a first principal surface 111 opposed in the thickness direction T, a second principal surface 112 opposed in the thickness direction T, and opposed to one principal surface of the core substrate B, a first end surface 113 and a second end surface 114 opposed to each other in the length direction L orthogonal or substantially orthogonal to the thickness direction T, and a first side surface 115 and a second side surface 116 opposed in the width direction W orthogonal or substantially orthogonal to the thickness direction T and the length direction L.

The laminated body 11 includes a cuboid or substantially cuboid outer shape, and may include at least one of corners and ridges rounded. The corner refers to the intersection of three surfaces of the laminated body, and the ridge refers to the intersection of two surfaces of the laminated body.

The first external electrode 12 and the second external electrode 13 are located on the surfaces at both ends in the length direction L.

Specifically, the first external electrode 12 is provided on the first end surface 113 of the laminated body 11, and extends from the first end surface 113 to respective portions of the first principal surface 111, the second principal surface 112, the first side surface 115, and the second side surface 116, and the second external electrode 13 is provided on the second end surface 114 of the laminated body 11, and extends from the second end surface 114 to respective portions of the first principal surface 111, the second principal surface 112, the first side surface 115, and the second side surface 116.

As shown in FIG. 2, of the mutually opposed internal electrode layers 15 and 16, one internal electrode layer 15 is electrically connected to the first external electrode 12 at the first end surface 113, and the other internal electrode layer 16 is electrically connected to the second external electrode 13 at the second end surface 114. More specifically, the first external electrode 12 is electrically connected to the one internal electrode layers 15 at the first end surface 113, and the second external electrode 13 is electrically connected to the other internal electrode layers 16 at the second end surface 114.

According to the present preferred embodiment, the internal electrode layers 15 and 16 are all electrically connected respectively to the first external electrode 12 and the second external electrode 13. However, in multilayer capacitor built-in substrates according to other preferred embodiments of the present invention, at least some of the plurality of internal electrode layers may be electrically connected to the first external electrode or the second external electrode. More specifically, the plurality of internal electrode layers may include an internal electrode layer that is not electrically connected to the first external electrode and the second external electrode.

As shown in FIGS. 2 and 3, the laminated body 11 includes an effective region E in which the internal electrode layers 15 and 16 respectively connected to the first external electrode 12 and the second external electrode 13 are laminated with the dielectric layers 14 located therebetween, and a non-effective region N surrounding the effective region E.

Specifically, the effective region E of the laminated body 11 refers to a region in which portions that define and function as a capacitor are laminated, each including the internal electrode layer 15 electrically connected to the first external electrode 12, the internal electrode layer 16 electrically connected to the second external electrode 13, and the dielectric layers 14 sandwiched between the two internal electrode layers 15 and 16.

In FIGS. 2 and 3, the effective region E of the laminated body 11 refers to an area in which all of the internal electrode layers 15 and 16 overlap each other as viewed in the thickness direction T in the area from an internal electrode layer located closest to the first principal surface 111 among the plurality of internal electrode layers 15 and 16 to an internal electrode layer located closest to the second principal surface 112 among the plurality of internal electrode layers 15 and 16.

The non-effective region N of the laminated body 11 is a portion located outside the effective region E in the laminated body 11, and is a region that does not define and function as a capacitor.

Examples of the material included in each of the plurality of dielectric layers 14 include dielectric ceramics containing, as their main components, BaTiO₃, CaTiO₃, SrTiO₃, CaZrO₃, or the like. Further, dielectric ceramics may include the foregoing main components with a Mn compound, a Mg compound, a Si compound, a Co compound, a Ni compound, a rare earth compound or the like added thereto as an accessory component.

Examples of the material included in each of the plurality of internal electrode layers 15 and 16 include a metal, for example, Ni, Cu, Ag, Pd, and Au, or an alloy containing at least one of these metals, for example, an alloy of Ag and Pd.

The first external electrode 12 and the second external electrode 13 each preferably include a base layer provided to cover both ends of the laminated body 11, and a plating layer provided to cover the base layer. Examples of the material included in the base layer include a metal, for example, Ni, Cu, Ag, Pd, and Au, or an alloy containing at least one of these metals, for example, an alloy of Ag and Pd.

Examples of a method of forming the base layer include, for example, a method of baking a conductive paste applied to both ends of the fired laminated body 11, or a method of co-firing a conductive paste applied to both ends of the unfired laminated body 11 at the same time as the internal electrode layer 15 and 16. Alternatively, a method of plating both ends of the laminated body 11 or a method of curing a conductive resin including a thermosetting resin applied to both ends of the laminated body 11 may be adopted.

Examples of the material included in the plating layer include a metal, for example, Sn, Ni, Cu, Ag, Pd, and Au, or an alloy containing at least one of these metals, for example, an alloy of Ag and Pd.

The plating layer may include multiple layers. In this case, the plating layer preferably includes a two-layer structure with a Sn plating layer formed on a Ni plating layer. The Ni plating layer defines and functions as a solder barrier layer. The Sn plating layer provides a favorable wettability to solder.

In the multilayer capacitor built-in substrate 1 shown in FIGS. 2 and 3, the multilayer ceramic capacitor 10 is mounted on the first land electrode L11 and the second land electrode L12 of the core substrate B.

Specifically, the first external electrode 12 and the second external electrode 13 of the multilayer ceramic capacitor 10 are electrically connected, with a solder, a conductive adhesive, or the like which are not shown, respectively to the first land electrode L11 and the second land electrode L12 of the core substrate B.

According to the first preferred embodiment, the thickness T_(R) of the burying layer is larger than the thickness T_(B) of the core substrate. Acoustic noise is able to be significantly reduced or prevented by defining the thickness T_(R) of the burying layer larger to be than the thickness T_(B) of the core substrate.

According to the first preferred embodiment, when the thickness of the burying layer and the thickness of the core substrate are denoted respectively by T_(R) and T_(B), the value of T_(R)/T_(B) is preferably about 1.25 or more, for example. In addition, the value of T_(R)/T_(B) is preferably about 2.50 or less, for example.

According to the first preferred embodiment, T_(C)<L_(L)/4 is satisfied when the distance between the first land electrode and the second land electrode in the length direction is denoted by L_(L), the height of the center of the effective region with the second principal surface of the laminated body as a reference plane is denoted by T_(C).

As shown in FIG. 2, the distance L_(L) between the first land electrode L11 and the second land electrode L12 is a length represented by a+b₁+b₂ when the interval between the first land electrode L11 and the second land electrode L12 is denoted by a, the length of the first land electrode L11 is denoted by b₁, and the length of the second land electrode L12 is denoted by b₂.

FIG. 4 is a cross-sectional view schematically illustrating an imaginary multilayer capacitor built-in substrate.

As shown in FIG. 4, in the imaginary multilayer capacitor built-in substrate 1′, it is assumed that the thickness T′ of a laminated body 11′ of a multilayer ceramic capacitor 10′ corresponds to the length represented by L_(L)/2, and the center of an effective region E′ coincides with the center of the laminated body 11′. In this case, T_(C)′=L_(L)/4 is satisfied when the height of the center of the effective region with the second principal surface of the laminated body as a reference plane is denoted by T_(C)′.

According to the first preferred embodiment, acoustic noise is able to be significantly reduced or prevented by satisfying T_(C)<L_(L)/4. It is to be noted that although there may be an interval between the laminated body and the core substrate, this interval is smaller than the value of T_(C), and thus considered as providing only a small influence on acoustic noise.

According to the first preferred embodiment, as shown in FIGS. 2 and 3, T_(C)<L_(L)/4 is satisfied by setting the height T_(C) of the center of the effective region E to about ¼ or less of the thickness T_(R) of the burying layer R, for example.

According to the first preferred embodiment, the height T_(C) of the center of the effective region is preferably about ⅕ or less of the thickness T_(R) of the burying layer, for example.

According to the first preferred embodiment, when the thickness of the laminated body is denoted by T, and the width of the laminated body is denoted by W, the value of T/W is preferably about ¾ or less, for example. In this specification, the maximum thickness of the laminated body in the thickness direction of the multilayer ceramic capacitor and the maximum width of the laminated body in the width direction are respectively denoted by T and W.

According to the first preferred embodiment, the thickness T of the laminated body is preferably about 0.33 mm or less, for example.

According to the first preferred embodiment of the present invention, as in a second preferred embodiment of the present invention to be described later, the thickness of the non-effective region closer to the second principal surface may be smaller than the thickness of the non-effective region closer to the first principal surface, but the thickness of the non-effective region closer to the second principal surface may be equal or substantially equal to the thickness of the non-effective region closer to the first principal surface, or the thickness of the non-effective region closer to the second principal surface may be larger than the thickness of the non-effective region closer to the first principal surface.

Second Preferred Embodiment

According to the second preferred embodiment of the present invention, the thickness T_(a) of the non-effective region closer to the second principal surface is smaller than the thickness T_(b) of the non-effective region closer to the first principal surface.

FIG. 5 is a cross-sectional view taken along the line X1-X1 of a multilayer capacitor built-in substrate according to the second preferred embodiment of the present invention. FIG. 6 is a cross-sectional view taken along the line Y1-Y1 of the multilayer capacitor built-in substrate according to the second preferred embodiment. It is to be noted that FIG. 5 corresponds to the cross-sectional view taken along the line X1-X1 of the multilayer capacitor built-in substrate shown in FIG. 1, and FIG. 6 corresponds to the cross-sectional view taken along the line Y1-Y1 of the multilayer capacitor built-in substrate shown in FIG. 1.

The multilayer capacitor built-in substrate 1A shown in FIGS. 5 and 6 includes a core substrate B, a multilayer ceramic capacitor 10A, and a burying layer R. The multilayer ceramic capacitor 10A is mounted on one principal surface of a core substrate B that includes one principal surface and the other principal surface parallel or substantially parallel to each other within the error range. The burying layer R is provided on one principal surface of the core substrate B to bury the multilayer ceramic capacitor 10A, and define the outer surface to be parallel or substantially parallel to the other principal surface of the core substrate B within the error range.

The multilayer capacitor built-in substrate according to the second preferred embodiment includes the same or similar features, components, and elements as the multilayer capacitor built-in substrate according to the first preferred embodiment, except that the multilayer ceramic capacitor includes different features, components, and elements as described herein.

According to the second preferred embodiment, the thickness T_(R) of the burying layer is larger than the thickness T_(B) of the core substrate. Acoustic noise is able to be significantly reduced or prevented by making the thickness T_(R) of the burying layer larger than the thickness T_(B) of the core substrate.

According to the second preferred embodiment, when the thickness of the burying layer and the thickness of the core substrate are denoted respectively by T_(R) and T_(B), the preferable range of the T_(R)/T_(B) value is the same as or similar to in the first preferred embodiment.

According to the second preferred embodiment, T_(C)<L_(L)/4 is satisfied when the distance between the first land electrode and the second land electrode in the length direction is denoted by L_(L), the height of the center of the effective region with the second principal surface of the laminated body as a reference plane is denoted by T_(C).

According to the second preferred embodiment, acoustic noise is able to be significantly reduced or prevented as in the first preferred embodiment by satisfying T_(C)<L_(L)/4.

According to the second preferred embodiment, as shown in FIGS. 5 and 6, T_(C)<L_(L)/4 is provided by making the thickness T_(a) of a non-effective region N_(A) closer to a second principal surface 112 smaller than the thickness T_(b) of the non-effective region N_(A) closer to a first principal surface 111.

FIGS. 7A, 7B and 7C are explanatory diagrams schematically illustrating an effective region and a non-effective region of a laminated body of a multilayer ceramic capacitor.

As shown in FIG. 7A, when the interval is regular between the internal electrode layer 15 electrically connected to the first external electrode 12 and the internal electrode layer 16 electrically connected to the second external electrode 13, an area in which all of the internal electrode layers 15 and 16 overlap each other as viewed in the thickness direction T in the area from an internal electrode layer located closest to the first principal surface 111 among the plurality of internal electrode layers 15 and 16 to an internal electrode layer located closest to the second principal surface 112 among the plurality of internal electrode layers 15 and 16 is referred to as an effective region E_(A) of a laminated body 11A. On the other hand, as shown in FIGS. 7B and 7C, when the interval is irregular between the internal electrode layer 15 electrically connected to the first external electrode 12 and the internal electrode layer 16 electrically connected to the second external electrode 13, areas where the internal electrode layers 15 and 16 overlap each other as viewed in the thickness direction T in the area from an internal electrode layer located closest to the first principal surface 111 among the plurality of internal electrode layers 15 and 16 to an internal electrode layer located closest to the second principal surface 112 among the plurality of internal electrode layers 15 and 16 are respectively referred to as an effective region E_(B) of a laminated body 11B and an effective region E_(C) of a laminated body 11C, provided that areas are ignored where the intervals are wider between the internal electrode layers 15 and the internal electrode layers 16. After defining the effective regions E_(A), E_(B) and E_(C) as mentioned above, the portions located outside the effective regions E_(A), E_(B) and E_(C) in the laminated bodies are respectively referred to as non-effective regions N_(A), N_(B) and N_(C). Even in the case of the first preferred embodiment, the effective region and non-effective region of the laminated body are able to be defined by the same method or a similar method.

For the measurement of various dimensions, a polished cross section of the multilayer capacitor built-in substrate is enlarged and then observed at, for example, 10-fold magnification with an optical microscope, and the dimension is measured on a straight line passing through the center of the polished cross section. When it is difficult to clearly measure the dimensions with the optical microscope, the polished cross section may be observed with a scanning electron microscope instead of the optical microscope.

For example, in the measurement of the thickness T_(a) of the non-effective region of the portions located between the second principal surface and the effective region in the laminated body, in an enlarged image of a cross section of the multilayer ceramic capacitor observed with an optical microscope, a straight line is drawn which extends in the laminating direction of the laminated body and passes through the center of the laminated body, and the thickness T_(a) of the non-effective region on the straight line is measured. Subsequently, in the case of measuring the thickness T_(B) of the core substrate and the thickness T_(R) of the burying layer, the thickness T_(B) of the core substrate and the thickness T_(R) of the burying layer are measured on the straight line.

The effective region of the laminated body is able to be confirmed by observing the polished cross section with an optical microscope in the same or a similar way as mentioned above. Alternatively, the effective region of the laminated body is able to be confirmed by observing a transmission image captured by irradiating the multilayer capacitor built-in substrate with X-rays from the first principal surface side or the second principal surface side.

A method of manufacturing the multilayer capacitor built-in substrate according to a preferred embodiment of the present invention will be described below.

A method of manufacturing the multilayer capacitor built-in substrate according to a preferred embodiment of the present invention includes the steps of preparing a multilayer capacitor, mounting the multilayer capacitor on one principal surface of a core substrate, and providing, on one principal surface of the core substrate, a burying layer that buries the multilayer capacitor.

This multilayer capacitor built-in substrate is able to be manufactured by, for example, the method described in Japanese Patent Application Laid-Open No. 2016-92176.

EXAMPLES

Examples that more specifically disclose multilayer capacitor built-in substrates according to the preferred embodiments of the present invention will be described below. It should be noted that the present invention is not to be considered limited to only these examples.

According to the following examples and comparative examples, the value of the distance L_(L) between the first land electrode and the second land electrode in the length direction is about 1.30 mm in Preferred Embodiment Example 1-1, Preferred Embodiment Example 1-2, Preferred Embodiment Example 1-3, and Preferred Embodiment Example 1-4, Preferred Embodiment Example 2-1, Comparative Example 1-1 and Comparative Example 2-1, and about 2.00 mm in Preferred Embodiment Example 1-5, Preferred Embodiment Example 1-6, Preferred Embodiment Example 2-2, Comparative Example 1-2 and Comparative Example 2-2.

In Preferred Embodiment Example 1-1, a multilayer ceramic capacitor with a laminated body of about 0.65 mm in width W and about 0.5 mm in thickness T was prepared, and mounted on one principal surface of a core substrate. Thereafter, a burying layer that buries the multilayer ceramic capacitor mentioned above was formed on one principal surface of the core substrate, thus providing a multilayer capacitor built-in substrate. The thickness T_(R) of the burying layer is about 1.0 mm, and the thickness T_(B) of the core substrate is about 0.8 mm.

According to Example 1-1, the height T_(C) of the center of the effective region is about 0.25 mm, and T_(C)<L_(L)/4 is thus satisfied.

In Preferred Embodiment Example 1-2, a multilayer capacitor built-in substrate was fabricated similar to Example 1-1, except that a multilayer ceramic capacitor with a laminated body thickness T of about 0.33 mm was prepared. According to Example 1-2, the height T_(C) of the center of the effective region is about 0.165 mm, and T_(C)<L_(L)/4 is thus satisfied.

In Preferred Embodiment Example 1-3, a multilayer capacitor built-in substrate was fabricated similar to Example 1-1, except that a multilayer ceramic capacitor with a laminated body thickness T of about 0.2 mm was prepared. According to Example 1-3, the height T_(C) of the center of the effective region is about 0.1 mm, and T_(C)<L_(L)/4 is thus satisfied.

In Preferred Embodiment Example 1-4, a multilayer capacitor built-in substrate was fabricated similar to Example 1-1, except that a multilayer ceramic capacitor with a laminated body thickness T of about 0.11 mm was prepared. According to Example 1-4, the height T_(C) of the center of the effective region is about 0.055 mm, and T_(C)<L_(L)/4 is thus satisfied.

In Comparative Example 1-1, a multilayer capacitor built-in substrate was fabricated similar to Example 1-1, except that a multilayer ceramic capacitor with a laminated body thickness T of about 0.65 mm was prepared. According to Comparative Example 1-1, the height T_(C) of the center of the effective region is about 0.325 mm, and T_(C)<_(LL)/4 is thus not satisfied.

In Preferred Embodiment Example 1-5, a multilayer ceramic capacitor with a laminated body of about 1.0 mm in width W and about 0.8 mm in thickness T was prepared, and mounted on one principal surface of a core substrate. Thereafter, a burying layer that buries the multilayer ceramic capacitor mentioned above was formed on one principal surface of the core substrate, thus providing a multilayer capacitor built-in substrate. The thickness T_(R) of the burying layer is about 1.2 mm, and the thickness T_(B) of the core substrate is about 0.8 mm. According to Example 1-5, the height T_(C) of the center of the effective region is about 0.4 mm, and T_(C)<L_(L)/4 is thus satisfied.

In Preferred Embodiment Example 1-6, a multilayer capacitor built-in substrate was fabricated similar to Example 1-5, except that a multilayer ceramic capacitor with a laminated body thickness T of about 0.6 mm was prepared. According to Example 1-6, the height T_(C) of the center of the effective region is about 0.3 mm, and T_(C)<L_(L)/4 is thus satisfied.

In Comparative Example 1-1, a multilayer capacitor built-in substrate was fabricated similar to Example 1-5, except that a multilayer ceramic capacitor with a laminated body thickness T of about 1.0 mm was prepared. According to Comparative Example 1-2, the height T_(C) of the center of the effective region is about 0.5 mm, and T_(C)<L_(L)/4 is thus not satisfied.

In Preferred Embodiment Example 2-1, a multilayer ceramic capacitor with a laminated body of about 0.65 mm in width W, about 0.65 mm in thickness T, about 0.03 mm in the thickness T_(a) of the non-effective region closer to the second principal surface, and about 0.15 mm in the thickness T_(b) of the non-effective region closer to the first principal surface was prepared, and mounted on one principal surface of a core substrate. Thereafter, a burying layer that buries the multilayer ceramic capacitor described above was provided on one principal surface of the core substrate, thus providing a multilayer capacitor built-in substrate. The thickness T_(R) of the burying layer is about 1.0 mm, and the thickness T_(B) of the core substrate is about 0.8 mm. According to Example 2-1, the height TC of the center of the effective region is about 0.315 mm, and T_(C)<L_(L)/4 is thus satisfied.

In Comparative Example 2-1, a multilayer capacitor built-in substrate was fabricated similar to Example 2-1, except that a multilayer ceramic capacitor of about 0.15 mm in the thickness T_(a) of the non-effective region closer to the second principal surface and about 0.03 mm in the thickness T_(b) of the non-effective region closer to the first principal surface was prepared. According to Comparative Example 2-1, the height TC of the center of the effective region is about 0.435 mm, and T_(C)<L_(L)/4 is thus not satisfied.

In Preferred Embodiment Example 2-2, a multilayer ceramic capacitor with a laminated body of about 1.0 mm in width W, about 1.0 mm in thickness T, about 0.04 mm in the thickness T_(a) of the non-effective region closer to the second principal surface, and about 0.15 mm in the thickness T_(b) of the non-effective region closer to the first principal surface was prepared, and mounted on one principal surface of a core substrate. Thereafter, a burying layer that buries the multilayer ceramic capacitor mentioned above was formed on one principal surface of the core substrate, thereby fabricating a multilayer capacitor built-in substrate. The thickness T_(R) of the burying layer is about 1.2 mm, and the thickness T_(B) of the core substrate is about 0.8 mm. According to Example 2-2, the height T_(C) of the center of the effective region is about 0.445 mm, and T_(C)<L_(L)/4 is thus satisfied.

In Comparative Example 2-2, a multilayer capacitor built-in substrate was fabricated similar to Example 2-2, except that a multilayer ceramic capacitor of about 0.15 mm in the thickness T_(a) of the non-effective region closer to the second principal surface and about 0.04 mm in the thickness T_(b) of the non-effective region closer to the first principal surface was prepared. According to Comparative Example 2-2, the height T_(C) of the center of the effective region is about 0.555 mm, and T_(C)<L_(L)/4 is thus not satisfied.

For each Preferred Embodiment Example and each Comparative Example, a reduction of acoustic noise was evaluated by measuring the sound pressure of noise generated from the multilayer capacitor built-in substrate.

FIG. 8 is a schematic diagram illustrating a method of measuring the sound pressure of noise generated from a multilayer capacitor built-in substrate.

As shown in FIG. 8, for the actual measurement of the sound pressure of noise, in the condition where a multilayer ceramic capacitor 10α was mounted on the core substrate B, and a multilayer capacitor built-in substrate 1α with the multilayer ceramic capacitor 10α buried in the burying layer R was set in an anechoic box 900, a direct-current voltage of 3.0 V and an alternating-current voltage of 1.0 Vpp in the frequency band of 1.5 kHz to 20 kHz were applied to the multilayer ceramic capacitor 10α, and the total sound pressure level of noise generated in that case was measured.

The total sound pressure level of noise was measured by providing a sound collecting microphone 910 in a location about 3 mm above the burying layer R in the anechoic box 900, collecting sounds produced from the multilayer capacitor built-in substrate 1α with the sound collecting microphone 910 and a sound collector 920, and analyzing the collected sounds by a FFT (Fast Fourier Transform) analyzer 930 (CF-5220 from ONO SOKKI Co., Ltd.).

Even in the condition where the multilayer ceramic capacitor 10 prepared according to each Preferred Embodiment Example and each Comparative Example was mounted on the core substrate B without including the burying layer R in place of the multilayer capacitor built-in substrate, in the same or a similar way as mentioned above, the voltages were applied to the multilayer ceramic capacitor, and the total sound pressure level of noise generated in that case was measured. In this regard, in the anechoic box 900, the sound collecting microphone 910 was provided in a location about 3 mm above the multilayer ceramic capacitor 10α.

FIG. 9 is a graph showing the results of measuring the sound pressure of noise in Preferred Embodiment Example 1-1, Preferred Embodiment Example 1-2, Preferred Embodiment Example 1-3, Preferred Embodiment Example 1-4, and Comparative Example 1-1. FIG. 10 is a graph showing the results of measuring the sound pressure of noise in Preferred Embodiment Example 1-5, Preferred Embodiment Example 1-6, and Comparative Example 1-2.

From FIGS. 9 and 10, it is able to be confirmed that in the condition where the burying layer that buries the multilayer ceramic capacitor is provided, the sound pressure of noise is significantly reduced when the multilayer ceramic capacitor is thin with respect to the burying layer.

FIG. 11 is a graph showing the results of measuring the sound pressure of noise in Preferred Embodiment Example 2-1 and Comparative Example 2-1. FIG. 12 is a graph showing the results of measuring the sound pressure of noise in Preferred Embodiment Example 2-2 and Comparative Example 2-2.

From FIGS. 11 and 12, it is able to be confirmed that in the condition where the burying layer that buries the multilayer ceramic capacitor is provided, the sound pressure of noise is significantly reduced when the thickness T_(a) of the non-effective region closer to the second principal surface is smaller than the thickness T_(b) of the non-effective region closer to the first principal surface.

While preferred embodiments of the present invention have been described above it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims. 

What is claimed is:
 1. A multilayer capacitor built-in substrate comprising: a core substrate; a multilayer capacitor mounted on one principal surface of the core substrate; and a burying layer provided on the one principal surface of the core substrate to bury the multilayer capacitor; wherein the multilayer capacitor includes a laminated body with a plurality of dielectric layers and a plurality of internal electrode layers laminated, a first external electrode, and a second external electrode; the laminated body includes: a first principal surface opposed in a thickness direction orthogonal or substantially orthogonal to the one principal surface of the core substrate; a second principal surface opposed in the thickness direction orthogonal or substantially orthogonal to the one principal surface of the core substrate and opposed to the one principal surface of the core substrate; a first end surface and a second end surface opposed in a length direction orthogonal or substantially orthogonal to the thickness direction; and a first side surface and a second side surface opposed in a width direction orthogonal or substantially orthogonal to the thickness direction and the length direction; the first external electrode is provided on the first end surface of the laminated body and electrically connected to at least some of the internal electrode layers of the plurality of internal electrode layers; the second external electrode is provided on the second end surface of the laminated body and electrically connected to at least some of the internal electrode layers of the plurality of internal electrode layers; the laminated body includes: an effective region where the internal electrode layers respectively connected to the first external electrode and the second external electrode are laminated with the dielectric layers located therebetween; and a non-effective region surrounding the effective region; the core substrate includes, on the one principal surface, a first land electrode electrically connected to the first external electrode and a second land electrode electrically connected to the first external electrode; a thickness T_(R) of the burying layer is larger than a thickness T_(B) of the core substrate; and T_(C)<L_(L)/4 is satisfied when a distance between the first land electrode and the second land electrode in the length direction is denoted by L_(L), and a height of a center of the effective region with the second principal surface of the laminated body as a reference plane is denoted by T_(C).
 2. The multilayer capacitor built-in substrate according to claim 1, wherein the height T_(C) of the center of the effective region is about ¼ or less of the thickness T_(R) of the burying layer.
 3. The multilayer capacitor built-in substrate according to claim 2, wherein a value of T/W is about ¾ or less when a thickness of the laminated body and a width of the laminated body are denoted respectively T and W.
 4. The multilayer capacitor built-in substrate according to claim 2, wherein a thickness T of the laminated body is about 0.33 mm or less.
 5. The multilayer capacitor built-in substrate according to claim 1, wherein a thickness T_(a) of the non-effective region closer to the second principal surface is smaller than a thickness T_(b) of the non-effective region closer to the first principal surface.
 6. The multilayer capacitor built-in substrate according to claim 1, wherein the burying layer causes the one principal surface of the core substrate to be parallel or substantially parallel to another principal surface of the core substrate.
 7. The multilayer capacitor built-in substrate according to claim 1, wherein the burying layer includes a resin material and a glass material.
 8. The multilayer capacitor built-in substrate according to claim 7, wherein the burying layer further includes a conductive material portion provided on a surface of the resin material.
 9. The multilayer capacitor built-in substrate according to claim 1, wherein the core layer substrate is a multilayer substrate.
 10. The multilayer capacitor built-in substrate according to claim 1, wherein at least one of the plurality of internal electrode layers is not connected to either the first external electrode or the second external electrode.
 11. The multilayer capacitor built-in substrate according to claim 1, wherein the effective region of the laminated body is defined by a cross-sectional area in the thickness direction in which all of the plurality of internal electrode layers overlap each other.
 12. The multilayer capacitor built-in substrate according to claim 1, wherein each of the plurality of dielectric layers includes a dielectric ceramic.
 13. The multilayer capacitor built-in substrate according to claim 1, wherein the first outer electrode includes a first base layer provided on the first end surface and a first plating layer that covers the first base layer; and the second outer electrode includes a second base layer provided on the second end surface and a second plating layer that covers the second base layer.
 14. The multilayer capacitor built-in substrate according to claim 13, wherein each of the first plating layer and the second plating layer includes a two-layer structure including an Sn plating layer and an Ni plating layer.
 15. The multilayer capacitor built-in substrate according to claim 1, wherein the multilayer capacitor is mounted on the one principal surface of the core substrate by a solder or a conductive adhesive that electrically connects the first land electrode to the first external electrode and electrically connects the second land electrode to the second external electrode.
 16. The multilayer capacitor built-in substrate according to claim 1, wherein a value of T_(R)/T_(B) is greater than about 1.25.
 17. The multilayer capacitor built-in substrate according to claim 1, wherein a value of T_(R)/T_(B) is less than about 2.50.
 18. The multilayer capacitor built-in substrate according to claim 2, wherein the height T_(C) of the center of the effective region is about ⅕ or less of the thickness T_(R) of the burying layer.
 19. The multilayer capacitor built-in substrate according to claim 1, wherein at least one of a corner portion and a ridge line portion of the multilayer body is rounded, the corner portion being defined by an intersection of three surfaces of the multilayer body and the ridge line portion being defined by an intersection of two surfaces of the multilayer body.
 20. The multilayer capacitor built-in substrate according to claim 1, wherein the laminated body includes a cuboid or substantially cuboid shape. 